Renesas Electronics, Buffert, 28 Ben, TSSOP

The Renesas Electronics zero delay buffer supports PCIe Gen1 and Gen2 clocking requirements. The is driven by a differential SRC output pair from an IDT compliant main clock generator. It attenuates jitter on the input clock and has a selectable PLL bandwidth to maximize performance in systems with or without Spread spectrum clocking. An SMBus interface allows control of the PLL bandwidth and bypass options, while 2 clock request pins make the suitable for Express card applications.

Selectable pll bandwidth minimizes jitter peaking in downstream plls