Infineon, CFI, SPI NOR 512 MB Flash-minne, 14.5 ns, 24 Ben, BGA, 4

This device connects to a host system via a Serial Peripheral Interface (SPI). Traditional SPI single bit serial input and output (SingleI/O or SIO) is supported as well as optional two bit (Dual I/O or DIO) and four bit (Quad I/O or QIO) serial commands. This multiplewidth interface is called SPI Multi-I/O or MIO. In addition, the FL-S family adds support for Double Data Rate (DDR) read commands for SIO, DIO and QIO that transfer address and read data on both edges of the clock.The Eclipse architecture features a Page Programming Buffer that allows up to 256 words (512 bytes) to be programmed in one operation, resulting in faster effective programming and erase than prior generation SPI program or erase algorithms. Executing code directly from flash memory is often called Execute-In-Place or XIP. By using FL-S devices at the higher clock rates supported, with QIO or DDR-QIO commands, the instruction read transfer rate can match or exceed traditional parallel interface,asynchronous, NOR flash memories while reducing signal count dramatically.The S25FL512S product offers high densities coupled with the flexibility and fast performance required by a variety of embedded applications. It is ideal for code shadowing, XIP and data storage.