Renesas Electronics 9DB233AGILF Clock Buffer 20-Pin TSSOP
- RS-artikelnummer:
- 263-7982
- Tillv. art.nr:
- 9DB233AGILF
- Tillverkare / varumärke:
- Renesas Electronics
Mängdrabatt möjlig
Antal (1 rör med 74 enheter)*
1 902,762 kr
(exkl. moms)
2 378,434 kr
(inkl. moms)
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- Dessutom levereras 74 enhet(er) från den 29 december 2025
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Enheter | Per enhet | Per Rør* |
|---|---|---|
| 74 - 222 | 25,713 kr | 1 902,76 kr |
| 296 + | 24,401 kr | 1 805,67 kr |
*vägledande pris
- RS-artikelnummer:
- 263-7982
- Tillv. art.nr:
- 9DB233AGILF
- Tillverkare / varumärke:
- Renesas Electronics
Specifikationer
Datablad
Lagstiftning och ursprungsland
Produktdetaljer
Hitta liknande produkter genom att välja ett eller flera attribut.
Välj alla | Attribut | Värde |
|---|---|---|
| Brand | Renesas Electronics | |
| Number of Elements per Chip | 4 | |
| Maximum Supply Current | 80 mA | |
| Maximum Input Frequency | 110MHz | |
| Mounting Type | SMD | |
| Package Type | TSSOP | |
| Pin Count | 20 | |
| Välj alla | ||
|---|---|---|
Brand Renesas Electronics | ||
Number of Elements per Chip 4 | ||
Maximum Supply Current 80 mA | ||
Maximum Input Frequency 110MHz | ||
Mounting Type SMD | ||
Package Type TSSOP | ||
Pin Count 20 | ||
- COO (Country of Origin):
- TW
The Renesas Electronics zero-delay buffer supports PCIe Gen1 and Gen2 clocking requirements. It is driven by a differential SRC output pair from an IDT main clock generator. It attenuates jitter on the input clock and has a selectable PLL bandwidth to maximize performance in systems with or without spread-spectrum clocking.
SMBus Interface
Selectable PLL bandwidth
Minimizes jitter peaking in downstream PLLs
Cycle-to-cycle jitter < 50ps
Output-to-output skew < 50 ps
PCIe Gen3 phase jitter < 1.0ps RMS
Selectable PLL bandwidth
Minimizes jitter peaking in downstream PLLs
Cycle-to-cycle jitter < 50ps
Output-to-output skew < 50 ps
PCIe Gen3 phase jitter < 1.0ps RMS
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