onsemi MC100EPT25DG, Logic Level Translator Translator ECL to LVTTL, 8-Pin SOIC-NB
- RS-artikelnummer:
- 186-9227
- Tillv. art.nr:
- MC100EPT25DG
- Tillverkare / varumärke:
- onsemi
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- RS-artikelnummer:
- 186-9227
- Tillv. art.nr:
- MC100EPT25DG
- Tillverkare / varumärke:
- onsemi
Specifikationer
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Välj alla | Attribut | Värde |
|---|---|---|
| Brand | onsemi | |
| Logic Family | ECL | |
| Mounting Type | Surface Mount | |
| Package Type | SOIC-NB | |
| Output Type | LVTTL | |
| Pin Count | 8 | |
| Logic Function | Translator | |
| Dimensions | 5 x 4 x 1.5mm | |
| Maximum Low Level Output Current | 24mA | |
| Maximum High Level Output Current | -3mA | |
| Translation | ECL to LVTTL | |
| Propagation Delay Test Condition | 20pF | |
| Maximum Propagation Delay Time @ Maximum CL | 1600 ps @ 20 pF | |
| Maximum Operating Supply Voltage | 3.6 V | |
| Maximum Operating Temperature | +85 °C | |
| Minimum Operating Supply Voltage | 3 V | |
| Minimum Operating Temperature | -40 °C | |
| Välj alla | ||
|---|---|---|
Brand onsemi | ||
Logic Family ECL | ||
Mounting Type Surface Mount | ||
Package Type SOIC-NB | ||
Output Type LVTTL | ||
Pin Count 8 | ||
Logic Function Translator | ||
Dimensions 5 x 4 x 1.5mm | ||
Maximum Low Level Output Current 24mA | ||
Maximum High Level Output Current -3mA | ||
Translation ECL to LVTTL | ||
Propagation Delay Test Condition 20pF | ||
Maximum Propagation Delay Time @ Maximum CL 1600 ps @ 20 pF | ||
Maximum Operating Supply Voltage 3.6 V | ||
Maximum Operating Temperature +85 °C | ||
Minimum Operating Supply Voltage 3 V | ||
Minimum Operating Temperature -40 °C | ||
The MC100EPT25 is a Differential LVECL/ECL to LVTTL translator. This device requires +3.3V, -3.3V to -5.2V, and ground. The small outline 8-lead SOIC package and the single gate of the EPT25 make it ideal for applications which require the translation of a clock or data signal.
The VBB output allows the EPT25 to also be used in a single-ended input mode. In this mode the VBB output is tied to the D input for a inverting buffer or the D input for a non-inverting buffer. If used, the VBB pin should be bypassed to ground with at least a 0.01 μF capacitor.
The VBB output allows the EPT25 to also be used in a single-ended input mode. In this mode the VBB output is tied to the D input for a inverting buffer or the D input for a non-inverting buffer. If used, the VBB pin should be bypassed to ground with at least a 0.01 μF capacitor.
1.1ns Typical Propagation Delay
Maximum Frequency > 275 MHz Typical
Operating Range: VCC = 3.0 V to 3.6 V, VEE = -5.5 V to -3.0 V, GND = 0 V
24mA TTL outputs
Q Output will default LOW with inputs open or at GND
VBB Output
Open Input Default State
Safety Clamp on Inputs
Pb-Free Packages are Available
Maximum Frequency > 275 MHz Typical
Operating Range: VCC = 3.0 V to 3.6 V, VEE = -5.5 V to -3.0 V, GND = 0 V
24mA TTL outputs
Q Output will default LOW with inputs open or at GND
VBB Output
Open Input Default State
Safety Clamp on Inputs
Pb-Free Packages are Available