Infineon SRAM, 4 MB, TSOP II 44 Ben

The Infineon Static RAM are high performance CMOS fast static RAM device with embedded ECC. This Static RAM device offered in single chip enable option and in multiple pin configurations. This device includes an ERR pin that signals an error detection and correction event during a read cycle. Data writes are performed by asserting the chip enable and write enable inputs LOW, while providing the data on IO 0 through IO 15 and address on A0 through A17 pins. The byte high enable and byte low enable inputs control write operations to the upper and lower bytes of the specified memory location.

High speed