Alliance Memory AS4C8M16SA-7TCN, SDRAM 128Mbit Surface Mount, 166MHz, 3 V to 3.6 V, 54-Pin TSOP
- RS-artikelnummer:
- 230-8442P
- Tillv. art.nr:
- AS4C8M16SA-7TCN
- Tillverkare / varumärke:
- Alliance Memory
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Antal 10 enheter (levereras på en bricka)*
283,35 kr
(exkl. moms)
354,19 kr
(inkl. moms)
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Enheter | Per enhet |
|---|---|
| 10 - 18 | 28,335 kr |
| 20 - 48 | 27,89 kr |
| 50 - 98 | 27,215 kr |
| 100 + | 24,92 kr |
*vägledande pris
- RS-artikelnummer:
- 230-8442P
- Tillv. art.nr:
- AS4C8M16SA-7TCN
- Tillverkare / varumärke:
- Alliance Memory
Specifikationer
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Lagstiftning och ursprungsland
Produktdetaljer
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Välj alla | Attribut | Värde |
|---|---|---|
| Brand | Alliance Memory | |
| Memory Size | 128Mbit | |
| Organisation | 8M x 16 | |
| SDRAM Class | DDR | |
| Data Rate | 166MHz | |
| Data Bus Width | 16bit | |
| Address Bus Width | 12bit | |
| Number of Bits per Word | 16bit | |
| Maximum Random Access Time | 5.4ns | |
| Number of Words | 8 M | |
| Mounting Type | Surface Mount | |
| Package Type | TSOP | |
| Pin Count | 54 | |
| Dimensions | 22.35 x 10.29 x 1.2mm | |
| Height | 1.2mm | |
| Length | 22.35mm | |
| Width | 10.29mm | |
| Minimum Operating Supply Voltage | 3 V | |
| Minimum Operating Temperature | 0 °C | |
| Maximum Operating Supply Voltage | 3.6 V | |
| Maximum Operating Temperature | +70 °C | |
| Välj alla | ||
|---|---|---|
Brand Alliance Memory | ||
Memory Size 128Mbit | ||
Organisation 8M x 16 | ||
SDRAM Class DDR | ||
Data Rate 166MHz | ||
Data Bus Width 16bit | ||
Address Bus Width 12bit | ||
Number of Bits per Word 16bit | ||
Maximum Random Access Time 5.4ns | ||
Number of Words 8 M | ||
Mounting Type Surface Mount | ||
Package Type TSOP | ||
Pin Count 54 | ||
Dimensions 22.35 x 10.29 x 1.2mm | ||
Height 1.2mm | ||
Length 22.35mm | ||
Width 10.29mm | ||
Minimum Operating Supply Voltage 3 V | ||
Minimum Operating Temperature 0 °C | ||
Maximum Operating Supply Voltage 3.6 V | ||
Maximum Operating Temperature +70 °C | ||
The Alliance Memory 128Mb SDRAM is a high-speed CMOS synchronous DRAM containing 128 Mbits. It is internally configured as 4 Banks of 2M word x 16 DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Read and write accesses to the SDRAM are burst oriented
accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of a BankActivate command which is then followed by a Read or Write command.
Auto Refresh and Self Refresh
4096 refresh cycles/64ms
CKE power down mode
Single +3.3V 0.3V power supply
Interface: LVTTL
4096 refresh cycles/64ms
CKE power down mode
Single +3.3V 0.3V power supply
Interface: LVTTL