Alliance Memory, SDRAM, 256 MB, Yta 16 bit, 70 °C, 0 °C, 54 Ben, TSOP

The Alliance Memory 256Mb SDRAM is a high-speed CMOS synchronous DRAM containing 256 Mbits. It is internally configured as 4 Banks of 4M word x 16 DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of a BankActivate command which is then followed by a Read or Write command.

Fast access time from clock: 5/5.4 ns