Microchip dsPIC33CK256MP508 FAMILY Mikroprocessor, 16 bit, CISC, dsPIC33CK CPU, 100 MHz, 64 Ben TQFP

Se alla Mikroprocessorer

Antal (1 fack med 160 enheter)*

3 262,56 kr

(exkl. moms)

4 078,24 kr

(inkl. moms)

Add to Basket
välj eller skriv kvantitet
Håller på att utgå
  • Slutlig(a) 160 enhet(er), redo att levereras
Enheter
Per enhet
Per fack*
160 +20,391 kr3 262,56 kr

*vägledande pris

RS-artikelnummer:
179-3964
Tillv. art.nr:
DSPIC33CK256MP506-I/PT
Tillverkare / varumärke:
Microchip
Hitta liknande produkter genom att välja ett eller flera attribut.
Välj alla

Varumärke

Microchip

Serie

dsPIC33CK256MP508 FAMILY

Produkttyp

Mikroprocessor

Enhetskärna

dsPIC33CK CPU

Databussbredd

16bit

Instruktionsuppsättning

CISC,

Maximal klockfrekvens

100MHz

Fästetyp

Yta

Kapseltyp

TQFP

Minsta matningsspänning

3.6V

Maximal matningsspänning

3.6V

Antal ben

64

Minsta arbetsstemperatur

-40°C

Maximal arbetstemperatur

85°C

Höjd

1.2mm

Längd

12mm

Bredd

12 mm

Standarder/godkännanden

IEC 60730, AEC-Q100 REVG (Grade 1)

Fordonsstandard

AEC-Q100

Antal kärnor

1

COO (ursprungsland):
US
Microchip’s dsPIC33CK family of digital signal controllers (DSCs) features a single 100 MIPS 16-bit dsPIC® DSC core with integrated DSP and enhanced on-chip peripherals. These DSCs enable the design of high-performance, precision motor control systems that are more energy efficient, quieter in operation and provide extended motor life. They can be used to control BLDC, PMSM, ACIM, SR and stepper motors.

3.0V to 3.6V, -40ºC to +125ºC, DC to 100 MIPS

dsPIC33CK DSC Core:

Modified Harvard architecture with 16-bit data and 24-bit instructions

Code efficient (C and Assembly) CPU architecture designed for real-time applications

16 16-bit working registers

4 sets of interrupt context saving registers, including ACC and CPU status for fast interrupt handling

Single-cycle, mixed-sign 32-bit MUL

Fast 6-cycle hardware 32/16 and 16/16 DIV

Dual 40-bit fixed point Accumulators (ACC) for DSP operations

Single-cycle MAC/MPY with dual data fetch and result write-back

Zero overhead looping support

Relaterade länkar