Infineon NOR 256 MB Quad-SPI Flash Memory 8-Pin WSON, S25FL256LAGNFM010
- RS-artikelnummer:
- 181-1605
- Tillv. art.nr:
- S25FL256LAGNFM010
- Tillverkare / varumärke:
- Infineon
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- RS-artikelnummer:
- 181-1605
- Tillv. art.nr:
- S25FL256LAGNFM010
- Tillverkare / varumärke:
- Infineon
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Välj alla | Attribut | Värde |
|---|---|---|
| Brand | Infineon | |
| Memory Size | 256MB | |
| Product Type | Flash Memory | |
| Interface Type | Quad-SPI | |
| Package Type | WSON | |
| Pin Count | 8 | |
| Organisation | 32M x 8 Bit | |
| Mount Type | Surface | |
| Maximum Clock Frequency | 133MHz | |
| Cell Type | NOR | |
| Maximum Supply Voltage | 3.6V | |
| Minimum Supply Voltage | 2.7V | |
| Timing Type | Synchronous | |
| Minimum Operating Temperature | -40°C | |
| Maximum Operating Temperature | 125°C | |
| Standards/Approvals | No | |
| Height | 1.9mm | |
| Length | 5.28mm | |
| Width | 8 mm | |
| Series | S25FL256L | |
| Automotive Standard | AEC-Q100 | |
| Number of Bits per Word | 8 | |
| Number of Words | 32M | |
| Maximum Random Access Time | 8ns | |
| Välj alla | ||
|---|---|---|
Brand Infineon | ||
Memory Size 256MB | ||
Product Type Flash Memory | ||
Interface Type Quad-SPI | ||
Package Type WSON | ||
Pin Count 8 | ||
Organisation 32M x 8 Bit | ||
Mount Type Surface | ||
Maximum Clock Frequency 133MHz | ||
Cell Type NOR | ||
Maximum Supply Voltage 3.6V | ||
Minimum Supply Voltage 2.7V | ||
Timing Type Synchronous | ||
Minimum Operating Temperature -40°C | ||
Maximum Operating Temperature 125°C | ||
Standards/Approvals No | ||
Height 1.9mm | ||
Length 5.28mm | ||
Width 8 mm | ||
Series S25FL256L | ||
Automotive Standard AEC-Q100 | ||
Number of Bits per Word 8 | ||
Number of Words 32M | ||
Maximum Random Access Time 8ns | ||
The FL-L family connects to a host system via a Serial Peripheral Interface (SPI). Traditional SPI single bit serial input and output (Single I/O or SIO) is supported as well as optional two bit (Dual I/O or DIO) and four bit wide Quad I/O (QIO) and Quad Peripheral Interface (QPI) commands. In addition, there are Double Data Rate (DDR) read commands for QIO and QPI that transfer address and read data on both edges of the clock. The architecture features a Page Programming Buffer that allows up to 256-bytes to be programmed in one operation and provides individual 4KB sector, 32KB half block, 64KB block, or entire chip erase. By using FL-L family devices at the higher clock rates supported, with Quad commands, the instruction read transfer rate can match or exceed traditional parallel interface, asynchronous, NOR Flash memories, while reducing signal count dramatically. The FL-L family products offer high densities coupled with the flexibility and fast performance required by a variety of mobile or embedded applications. Provides an ideal storage solution for systems with limited space, signal connections, and power.
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