Microchip, 16 bit DSPIC33EV AEC-Q100 Rev G Grad 1, AEC-Q100 Rev G Grad 0, Digital signalprocessor, 70 MHz, 256kB Flash,

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Förpackningsalternativ:
RS-artikelnummer:
869-6110P
Tillv. art.nr:
DSPIC33EV256GM104-I/PT
Tillverkare / varumärke:
Microchip
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Varumärke

Microchip

Maximal klockfrekvens

70MHz

Produkttyp

Digital signalprocessor

Serie

DSPIC33EV

Enhet MIPS

70MIPS

Databussbredd

16bit

RAM-storlek

16kB

Kärna

dsPIC33E

Instruktionsuppsättning

C

Programminnesstorlek

256kB

Programminnestyp

Flash

Minsta matningsspänning

4.5V

Typ av fäste

Yta

Maximal matningsspänning

5.5V

Antal PWM-kanaler

6

Kapseltyp

TQFP

Minsta arbetsstemperatur

-40°C

Antal ADC:er

1

Maximal arbetstemperatur

85°C

Antal ben

44

Längd

10mm

Standarder/godkännanden

AEC-Q100, IEC 60730

Höjd

1.1mm

PWM-upplösning

7.14ns

Fordonsstandard

AEC-Q100 Rev G Grad 1, AEC-Q100 Rev G Grad 0

Antal PWM-enheter

3

ADC-kanaler

1

ADC-upplösning

12bit

Timerupplösning

32bit

Antal kärnor

1

dsPIC33EVxxxGM00x/10x 16-Bit Digital Signal Controllers


Microchip’s dsPIC33EV family of 16-bit Digital Signal Controllers (DSCs) features a 70 MIPS dsPIC® DSC core with enhanced on-chip features. Capable of operating in harsh environments these devices are suitable for appliance and automotive applications. Rich peripheral integration includes SENT (Single-Edge Nibble Transmission-Transmit/Receive), High Speed PWMs, OP Amps and Error Correcting Code Flash for increased reliability and safety. The performance offered by the dsPIC33EV family of MCUs allows them to be incorporated into the design of high-performance, precision motor control systems that are more energy efficient. They can be used to control BLDC, permanent magnet synchronous, AC induction and stepper motors.

Microcontroller Features


70 MHz Max. CPU Speed

Code-Efficient (C and Assembly) Architecture

16-Bit Wide Data Path

Two 40-Bit Wide Accumulators

Single-Cycle (MAC/MPY) with Dual Data Fetch

Single-Cycle, Mixed-Sign MUL plus Hardware Divide

32-Bit Multiply Support

Intermediate Security for Memory - Provides a Boot Flash Segment in addition to the existing General Flash Segment

Error Code Correction (ECC) for Flash

Added Two Alternate Register Sets for Fast Context Switching

Clock Management Features


Internal, 15% Low-Power RC (LPRC) – 32 kHz

Internal, 1% Fast RC (FRC) – 7.37 MHz

Internal, 10% Backup RC (BFRC) – 7.37 MHz

Programmable PLLs and Oscillator Clock Sources

Fail-Safe Clock Monitor (FSCM)

Additional Fail-Safe Clock Monitor Source (BFRC), Intended to Provide a Clock Fail Switch Source for the System Clock

Independent Watchdog Timer (WDT)

System Windowed Watchdog Timer (DMT)

Fast Wake-Up and Start-Up

Power Management Features


Low-Power Management modes (Sleep, Idle and Doze)

Power Consumption Minimized Executing NOP String

Integrated Power-on Reset (POR) and Brown-out Reset (BOR)

0.5 mA/MHz Dynamic Current (typical)

50 μA at +25°C IPD Current (typical)

Peripheral Features


Up to Six Pulse-Width Modulation (PWM) Outputs (three generators)

Configurable Analogue to Digital Converter (ADC) Module

Up to 4 Operational Amplifiers

Up to 5 Comparators

Charge Time Measurement Unit (CTMU) - Supports mTouch™ capacitive touch sensing

Five 16-bit Timers

Two 32-bit Timers

Four Output Capture modules Configurable as Timers/Counters

Four Input Capture modules

Two Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART)

Two SPI Modules

One I2C Module with SMBus Support