854S006AGILF, Clock Buffer LVDS, 2-Input, 24-Pin SOIC
- RS-artikelnummer:
- 216-6214
- Tillv. art.nr:
- 854S006AGILF
- Tillverkare / varumärke:
- Renesas Electronics
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Antal (1 enhet)*
244,45 kr
(exkl. moms)
305,56 kr
(inkl. moms)
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- Dessutom levereras 65 enhet(er) från den 20 januari 2026
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Enheter | Per enhet |
|---|---|
| 1 - 9 | 244,45 kr |
| 10 - 24 | 224,56 kr |
| 25 - 49 | 215,04 kr |
| 50 - 99 | 207,09 kr |
| 100 + | 189,84 kr |
*vägledande pris
- RS-artikelnummer:
- 216-6214
- Tillv. art.nr:
- 854S006AGILF
- Tillverkare / varumärke:
- Renesas Electronics
Specifikationer
Datablad
Lagstiftning och ursprungsland
Produktdetaljer
Hitta liknande produkter genom att välja ett eller flera attribut.
Välj alla | Attribut | Värde |
|---|---|---|
| Brand | Renesas Electronics | |
| Logic Family | LVDS | |
| Logic Function | Clock Buffer | |
| Input Signal Type | LVDS | |
| Number of Clock Inputs | 2 | |
| Package Type | SOIC | |
| Pin Count | 24 | |
| Välj alla | ||
|---|---|---|
Brand Renesas Electronics | ||
Logic Family LVDS | ||
Logic Function Clock Buffer | ||
Input Signal Type LVDS | ||
Number of Clock Inputs 2 | ||
Package Type SOIC | ||
Pin Count 24 | ||
The Renesas Electronics 854S006 is a low skew, high performance 1-to-6, Differential-to-LVDS fanout buffer. The CLK, nCLK pair can accept most standard differential input levels. The 854S006 is characterized to operate from either a 2.5V or a 3.3V power supply. Guaranteed output and part-to-part skew characteristics make the 854S006 ideal for those clock distribution applications demanding well defined performance and repeatability.
Six differential LVDS outputs
One differential clock input pair
CLK, nCLK pair can accept the following differential input
levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
Maximum output frequency: 1.7GHz
Translates any single-ended input signal to LVDS levels with
resistor bias on nCLK input
Output Skew: 55ps (maximum)
Propagation delay: 850ps (maximum)
Additive phase jitter, RMS: 0.067ps (typical)
Full 3.3V or 2.5V supply
-40°C to 85°C ambient operating temperature
One differential clock input pair
CLK, nCLK pair can accept the following differential input
levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
Maximum output frequency: 1.7GHz
Translates any single-ended input signal to LVDS levels with
resistor bias on nCLK input
Output Skew: 55ps (maximum)
Propagation delay: 850ps (maximum)
Additive phase jitter, RMS: 0.067ps (typical)
Full 3.3V or 2.5V supply
-40°C to 85°C ambient operating temperature