853S011BGILF, Clock Buffer, 2-Input, 8-Pin SOIC
- RS-artikelnummer:
- 216-6211
- Tillv. art.nr:
- 853S011BGILF
- Tillverkare / varumärke:
- Renesas Electronics
Antal (1 rör med 96 enheter)*
3 415,392 kr
(exkl. moms)
4 269,216 kr
(inkl. moms)
GRATIS leverans för online beställningar över 500,00 kr
I lager
- Dessutom levereras 96 enhet(er) från den 06 januari 2026
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Enheter | Per enhet | Per Rør* |
|---|---|---|
| 96 + | 35,577 kr | 3 415,39 kr |
*vägledande pris
- RS-artikelnummer:
- 216-6211
- Tillv. art.nr:
- 853S011BGILF
- Tillverkare / varumärke:
- Renesas Electronics
Specifikationer
Datablad
Lagstiftning och ursprungsland
Produktdetaljer
Hitta liknande produkter genom att välja ett eller flera attribut.
Välj alla | Attribut | Värde |
|---|---|---|
| Brand | Renesas Electronics | |
| Logic Function | Clock Buffer | |
| Input Signal Type | LVPECL | |
| Number of Clock Inputs | 2 | |
| Package Type | SOIC | |
| Pin Count | 8 | |
| Välj alla | ||
|---|---|---|
Brand Renesas Electronics | ||
Logic Function Clock Buffer | ||
Input Signal Type LVPECL | ||
Number of Clock Inputs 2 | ||
Package Type SOIC | ||
Pin Count 8 | ||
The Renesas Electronics 853S011B is a low skew, high performance 1-to-2 Differential-to-2.5V/3.3V LVPECL/ECL Fanout Buffer. The 853S011B is characterized to operate from either a 2.5V or a 3.3V power supply. Guaranteed output and part-to-part skew characteristics make the 853S011B ideal for those clock distribution applications demanding well defined performance and repeatability.
Two differential 2.5V, 3.3V LVPECL/ECL outputs
One differential PCLK, nPCLK input pair
PCLK, nPCLK pairs can accept the following
differential input levels: LVPECL, LVDS, CML, SSTL
Maximum output frequency: >2.5GHz
Translates any single-ended input signal to 3.3V LVPECL levels
with resistor bias on nPCLK input
Output skew: 5ps (typical)
Part-to-part skew: 130ps (maximum)
Propagation delay: 355ps (maximum)
One differential PCLK, nPCLK input pair
PCLK, nPCLK pairs can accept the following
differential input levels: LVPECL, LVDS, CML, SSTL
Maximum output frequency: >2.5GHz
Translates any single-ended input signal to 3.3V LVPECL levels
with resistor bias on nPCLK input
Output skew: 5ps (typical)
Part-to-part skew: 130ps (maximum)
Propagation delay: 355ps (maximum)
