Renesas Electronics 9DB633AGILF Clock Buffer 28-Pin TSSOP
- RS-artikelnummer:
- 263-7988
- Tillv. art.nr:
- 9DB633AGILF
- Tillverkare / varumärke:
- Renesas Electronics
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58,02 kr
(exkl. moms)
72,52 kr
(inkl. moms)
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Enheter | Per enhet |
|---|---|
| 1 - 9 | 58,02 kr |
| 10 - 24 | 52,19 kr |
| 25 - 49 | 51,07 kr |
| 50 - 99 | 49,50 kr |
| 100 + | 42,78 kr |
*vägledande pris
- RS-artikelnummer:
- 263-7988
- Tillv. art.nr:
- 9DB633AGILF
- Tillverkare / varumärke:
- Renesas Electronics
Specifikationer
Datablad
Lagstiftning och ursprungsland
Produktdetaljer
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Välj alla | Attribut | Värde |
|---|---|---|
| Brand | Renesas Electronics | |
| Number of Elements per Chip | 5 | |
| Maximum Supply Current | 200 μA | |
| Maximum Input Frequency | 110MHz | |
| Mounting Type | Surface Mount | |
| Package Type | TSSOP | |
| Pin Count | 28 | |
| Välj alla | ||
|---|---|---|
Brand Renesas Electronics | ||
Number of Elements per Chip 5 | ||
Maximum Supply Current 200 μA | ||
Maximum Input Frequency 110MHz | ||
Mounting Type Surface Mount | ||
Package Type TSSOP | ||
Pin Count 28 | ||
- COO (Country of Origin):
- TW
The Renesas Electronics zero-delay buffer supports PCIe Gen1 and Gen2 clocking requirements. It is driven by a differential SRC output pair from an IDT main clock generator. It attenuates jitter on the input clock and has a selectable PLL bandwidth to maximize performance in systems with or without spread-spectrum clocking.
SMBus Interface
Selectable PLL bandwidth
Minimizes jitter peaking in downstream PLLs
Cycle-to-cycle jitter < 50ps
Output-to-output skew < 50 ps
PCIe Gen3 phase jitter < 1.0ps RMS
Selectable PLL bandwidth
Minimizes jitter peaking in downstream PLLs
Cycle-to-cycle jitter < 50ps
Output-to-output skew < 50 ps
PCIe Gen3 phase jitter < 1.0ps RMS
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