Nexperia 74HCT373D,653, Octal Octal D Type Latch, 8-Bit Non-Inverting, 20-Pin SO-20
- RS-artikelnummer:
- 170-4869
- Tillv. art.nr:
- 74HCT373D,653
- Tillverkare / varumärke:
- Nexperia
Antal (1 rulle med 2000 enheter)*
9 116,00 kr
(exkl. moms)
11 396,00 kr
(inkl. moms)
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- 2 000 enhet(er) levereras från den 06 maj 2026
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Enheter | Per enhet | Per rulle* |
|---|---|---|
| 2000 + | 4,558 kr | 9 116,00 kr |
*vägledande pris
- RS-artikelnummer:
- 170-4869
- Tillv. art.nr:
- 74HCT373D,653
- Tillverkare / varumärke:
- Nexperia
Specifikationer
Datablad
Lagstiftning och ursprungsland
Produktdetaljer
Hitta liknande produkter genom att välja ett eller flera attribut.
Välj alla | Attribut | Värde |
|---|---|---|
| Brand | Nexperia | |
| Logic Family | 74HCT | |
| Logic Function | D Type | |
| Number of Elements per Chip | 8 | |
| Number of Channels per Chip | 8 | |
| Polarity | Non-Inverting | |
| Mounting Type | Surface Mount | |
| Package Type | SO-20 | |
| Pin Count | 20 | |
| Width | 7.6mm | |
| Maximum Operating Supply Voltage | 5.5 V | |
| Length | 13mm | |
| Minimum Operating Temperature | -40 °C | |
| Dimensions | 13 x 7.6 x 2.45mm | |
| Minimum Operating Supply Voltage | 4.5 V | |
| Maximum Operating Temperature | +125 °C | |
| Height | 2.45mm | |
| Välj alla | ||
|---|---|---|
Brand Nexperia | ||
Logic Family 74HCT | ||
Logic Function D Type | ||
Number of Elements per Chip 8 | ||
Number of Channels per Chip 8 | ||
Polarity Non-Inverting | ||
Mounting Type Surface Mount | ||
Package Type SO-20 | ||
Pin Count 20 | ||
Width 7.6mm | ||
Maximum Operating Supply Voltage 5.5 V | ||
Length 13mm | ||
Minimum Operating Temperature -40 °C | ||
Dimensions 13 x 7.6 x 2.45mm | ||
Minimum Operating Supply Voltage 4.5 V | ||
Maximum Operating Temperature +125 °C | ||
Height 2.45mm | ||
- COO (Country of Origin):
- CN
The 74HC373, 74HCT373 is an octal D-type transparent latch with 3-state outputs. The device features latch enable (LE) and output enable (OE) inputs. When LE is HIGH, data at the inputs enter the latches. In this condition the latches are transparent, a latch output will change each time its corresponding D-input changes. When LE is LOW the latches store the information that was present at the inputs a set-up time preceding the HIGH-to-LOW transition of LE.
Mixed 5 V and 3.3 V applications
Save board space
Low cost interface solutions
Improved signal integrity for complex layouts
Wide supply voltage range
Low propagation delay
Overvoltage tolerant
Source termination
Low input threshold
CMOS low power
Key applications
Memory controllers
Backplane interfaces
Save board space
Low cost interface solutions
Improved signal integrity for complex layouts
Wide supply voltage range
Low propagation delay
Overvoltage tolerant
Source termination
Low input threshold
CMOS low power
Key applications
Memory controllers
Backplane interfaces
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