STMicroelectronics STM32MP233CAJ3 ARM Cortex A35, ARM Cortex M33 Microprocessor STM32MP23xC/F 16 bit ARM V8-A, ARM V8-M
- RS-artikelnummer:
- 482-987
- Tillv. art.nr:
- STM32MP233CAJ3
- Tillverkare / varumärke:
- STMicroelectronics
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- RS-artikelnummer:
- 482-987
- Tillv. art.nr:
- STM32MP233CAJ3
- Tillverkare / varumärke:
- STMicroelectronics
Specifikationer
Datablad
Lagstiftning och ursprungsland
Produktdetaljer
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Välj alla | Attribut | Värde |
|---|---|---|
| Brand | STMicroelectronics | |
| Series | STM32MP23xC/F | |
| Product Type | Microprocessor | |
| Device Core | ARM Cortex A35, ARM Cortex M33 | |
| Data Bus Width | 16bit | |
| Instruction Set Architecture | ARM V8-A, ARM V8-M | |
| Maximum Clock Frequency | 1.5GHz | |
| Interface Type | I2S, Parallel, LPDDR4, I3C, I2C, FMC, Ethernet, DDR4, DDR3L, CAN FD, UART, SPDIF RX, SPI, SDM, SAI, USB 2.0, USART | |
| Minimum Supply Voltage | 1.71V | |
| Package Type | TFBGA361 | |
| Maximum Supply Voltage | 3.6V | |
| Pin Count | 361 | |
| Standards/Approvals | ECOPACK2, JEDEC | |
| Automotive Standard | No | |
| Number of Cores | 2 | |
| Välj alla | ||
|---|---|---|
Brand STMicroelectronics | ||
Series STM32MP23xC/F | ||
Product Type Microprocessor | ||
Device Core ARM Cortex A35, ARM Cortex M33 | ||
Data Bus Width 16bit | ||
Instruction Set Architecture ARM V8-A, ARM V8-M | ||
Maximum Clock Frequency 1.5GHz | ||
Interface Type I2S, Parallel, LPDDR4, I3C, I2C, FMC, Ethernet, DDR4, DDR3L, CAN FD, UART, SPDIF RX, SPI, SDM, SAI, USB 2.0, USART | ||
Minimum Supply Voltage 1.71V | ||
Package Type TFBGA361 | ||
Maximum Supply Voltage 3.6V | ||
Pin Count 361 | ||
Standards/Approvals ECOPACK2, JEDEC | ||
Automotive Standard No | ||
Number of Cores 2 | ||
- COO (Country of Origin):
- TW
The STMicroelectronics MPU with Dual Arm Cortex-A35 devices are based on the high-performance single or dual-core Arm Cortex-A35 64-bit RISC core operating at up to 1.5 GHz. The Cortex‑A35 processor includes a 32-Kbyte L1 instruction cache for each CPU, a 32-Kbyte L1 data cache for each CPU, and a 512-Kbyte L2 cache. The Cortex‑A35 processor uses a highly efficient 8-stage in-order pipeline that has been extensively optimized to provide full Armv8-A features while maximizing area and power efficiency.
Internal temperature sensors
Low power consumption
Clock management
Digital parallel interface up to 16 bit input or output
Two Octo-SPI memory interfaces
DDR memory retention in Standby mode
Controls for PMIC companion chip
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