Nexperia 2-Input AND Schmitt Trigger Input Logic Gate, 5-Pin TSSOP-5
- RS-artikelnummer:
- 240-1725P
- Tillv. art.nr:
- 74AUP1T08GW-Q100H
- Tillverkare / varumärke:
- Nexperia
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- 2 975 enhet(er) levereras från den 03 juni 2026
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Enheter | Per enhet |
|---|---|
| 50 - 75 | 5,166 kr |
| 100 - 225 | 3,942 kr |
| 250 - 975 | 3,871 kr |
| 1000 + | 2,392 kr |
*vägledande pris
- RS-artikelnummer:
- 240-1725P
- Tillv. art.nr:
- 74AUP1T08GW-Q100H
- Tillverkare / varumärke:
- Nexperia
Specifikationer
Datablad
Lagstiftning och ursprungsland
Produktdetaljer
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Välj alla | Attribut | Värde |
|---|---|---|
| Brand | Nexperia | |
| Logic Function | AND | |
| Product Type | Logic Gate | |
| Mount Type | Surface | |
| Number of Inputs per Gate | 2 | |
| Schmitt Trigger Input | Yes | |
| Package Type | TSSOP-5 | |
| Pin Count | 5 | |
| Logic Family | AUP | |
| Minimum Operating Temperature | -40°C | |
| Maximum High Level Output Current | -4mA | |
| Maximum Propagation Delay Time @ CL | 4.8ns | |
| Maximum Operating Temperature | 125°C | |
| Minimum Supply Voltage | 2.3V | |
| Width | 1.35 mm | |
| Maximum Supply Voltage | 3.6V | |
| Standards/Approvals | No | |
| Height | 1.1mm | |
| Length | 2.25mm | |
| Maximum Low Level Output Current | 4mA | |
| Automotive Standard | AEC-Q100 | |
| Välj alla | ||
|---|---|---|
Brand Nexperia | ||
Logic Function AND | ||
Product Type Logic Gate | ||
Mount Type Surface | ||
Number of Inputs per Gate 2 | ||
Schmitt Trigger Input Yes | ||
Package Type TSSOP-5 | ||
Pin Count 5 | ||
Logic Family AUP | ||
Minimum Operating Temperature -40°C | ||
Maximum High Level Output Current -4mA | ||
Maximum Propagation Delay Time @ CL 4.8ns | ||
Maximum Operating Temperature 125°C | ||
Minimum Supply Voltage 2.3V | ||
Width 1.35 mm | ||
Maximum Supply Voltage 3.6V | ||
Standards/Approvals No | ||
Height 1.1mm | ||
Length 2.25mm | ||
Maximum Low Level Output Current 4mA | ||
Automotive Standard AEC-Q100 | ||
The Nexperia low-power 2 input AND gate with voltage-level translator provides the single 2-input AND function. This device ensures a very low static and dynamic power consumption across the entire VCC range from 2.3 V to 3.6 V. It is designed for logic-l
Low static power consumption; ICC1.5 μA (maximum)
Latch-up performance exceeds 100 mA per JESD 78 Class II
Inputs accept voltages up to 3.6 V
Low noise overshoot and undershoot < 10 % of VCC
IOFF circuitry provides partial power-down mode operation