Toshiba, 2 4-Input NAND CMOS Digital Integrated Circuit, 14-Pin TSSOP
- RS-artikelnummer:
- 171-3421P
- Tillv. art.nr:
- 74VHC20FT
- Tillverkare / varumärke:
- Toshiba
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- RS-artikelnummer:
- 171-3421P
- Tillv. art.nr:
- 74VHC20FT
- Tillverkare / varumärke:
- Toshiba
Specifikationer
Datablad
Lagstiftning och ursprungsland
Produktdetaljer
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Välj alla | Attribut | Värde |
|---|---|---|
| Brand | Toshiba | |
| Product Type | CMOS Digital Integrated Circuit | |
| Logic Function | NAND | |
| Mount Type | Surface | |
| Number of Elements | 2 | |
| Number of Inputs per Gate | 4 | |
| Schmitt Trigger Input | No | |
| Package Type | TSSOP | |
| Pin Count | 14 | |
| Logic Family | 74VHC | |
| Input Type | CMOS, TTL | |
| Minimum Operating Temperature | -40°C | |
| Maximum High Level Output Current | -8mA | |
| Maximum Propagation Delay Time @ CL | 13ns | |
| Maximum Operating Temperature | 125°C | |
| Height | 1mm | |
| Series | 74VHC | |
| Width | 4.4 mm | |
| Minimum Supply Voltage | 2V | |
| Standards/Approvals | AEC-Q100 | |
| Maximum Supply Voltage | 5.5V | |
| Length | 5mm | |
| Maximum Low Level Output Current | 8mA | |
| Output Type | CMOS, Buffer | |
| Automotive Standard | AEC-Q100 | |
| Välj alla | ||
|---|---|---|
Brand Toshiba | ||
Product Type CMOS Digital Integrated Circuit | ||
Logic Function NAND | ||
Mount Type Surface | ||
Number of Elements 2 | ||
Number of Inputs per Gate 4 | ||
Schmitt Trigger Input No | ||
Package Type TSSOP | ||
Pin Count 14 | ||
Logic Family 74VHC | ||
Input Type CMOS, TTL | ||
Minimum Operating Temperature -40°C | ||
Maximum High Level Output Current -8mA | ||
Maximum Propagation Delay Time @ CL 13ns | ||
Maximum Operating Temperature 125°C | ||
Height 1mm | ||
Series 74VHC | ||
Width 4.4 mm | ||
Minimum Supply Voltage 2V | ||
Standards/Approvals AEC-Q100 | ||
Maximum Supply Voltage 5.5V | ||
Length 5mm | ||
Maximum Low Level Output Current 8mA | ||
Output Type CMOS, Buffer | ||
Automotive Standard AEC-Q100 | ||
The 74VHC20FT is an advanced high speed CMOS 4-INPUT NAND GATE fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. The internal circuit is composed of 3 stages including a buffer output, which provide high noise immunity and stable output. An input protection circuit ensures that 0 to 5.5 V can be applied to the input pins without regard to the supply voltage. This device can be used to interface 5 V to 3 V systems and two supply systems such as battery back up. This circuit prevents device destruction due to mismatched supply and input voltages.
Wide operating temperature: Topr = -40 to 125
High speed: tpd = 3.3 ns (typ.) at VCC = 5.0 V
Low power dissipation: ICC = 2.0 μA (max) at Ta = 25
High noise immunity: VNIH = VNIL = 28 % VCC (min)
Power down protection is provided on all inputs.
Balanced propagation delays: tPLH ≈ tPHL
Wide operating voltage range: VCC(opr) = 2.0 V to 5.5 V
Pin and function compatible with the 74 series (AC/HC/AHC/LV etc.) 20 type