Nexperia 74AUP2G08DC,125, Dual 2-Input AND Schmitt Trigger Logic Gate, 8-Pin VSSOP

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25 - 2252,572 kr64,30 kr
250 - 6002,50 kr62,50 kr
625 - 12252,437 kr60,93 kr
1250 - 24752,37 kr59,25 kr
2500 +2,312 kr57,80 kr

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Förpackningsalternativ:
RS-artikelnummer:
153-2935
Tillv. art.nr:
74AUP2G08DC,125
Tillverkare / varumärke:
Nexperia
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Brand

Nexperia

Logic Function

AND

Mounting Type

Surface Mount

Number of Elements

2

Number of Inputs per Gate

2

Schmitt Trigger Input

Yes

Package Type

VSSOP

Pin Count

8

Logic Family

AUP

Input Type

CMOS

Maximum Operating Supply Voltage

3.6 V

Maximum High Level Output Current

-4mA

Maximum Propagation Delay Time @ Maximum CL

24 @ 30 pF

Minimum Operating Supply Voltage

0.8 V

Maximum Low Level Output Current

4mA

Maximum Operating Temperature

+125 °C

Dimensions

2.1 x 2.4 x 0.85mm

Propagation Delay Test Condition

30pF

Output Type

ECL

Minimum Operating Temperature

-40 °C

Length

2.1mm

Width

2.4mm

Height

0.85mm

Low-power dual 2-input AND gate, The 74AUP2G08 provides the dual 2-input AND function. Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V. This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing a damaging backflow current through the device when it is powered down.

Wide supply voltage range from 0.8 V to 3.6 V
High noise immunity
Low static power consumption, ICC = 0.9 μA (maximum)
Latch-up performance exceeds 100 mA per JESD78 Class II
Inputs accept voltages up to 3.6 V
Low noise overshoot and undershoot < 10 % of VCC
IOFF circuitry provides partial power-down mode operation
Multiple package options

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