Infineon NOR 128 MB Quad-SPI Flash Memory 8-Pin SOIC, S25FL128LAGMFV010
- RS-artikelnummer:
- 181-1589
- Tillv. art.nr:
- S25FL128LAGMFV010
- Tillverkare / varumärke:
- Infineon
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| 3 + | 22,177 kr | 66,53 kr |
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- RS-artikelnummer:
- 181-1589
- Tillv. art.nr:
- S25FL128LAGMFV010
- Tillverkare / varumärke:
- Infineon
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Produktdetaljer
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Välj alla | Attribut | Värde |
|---|---|---|
| Brand | Infineon | |
| Product Type | Flash Memory | |
| Memory Size | 128MB | |
| Interface Type | Quad-SPI | |
| Package Type | SOIC | |
| Pin Count | 8 | |
| Organisation | 16M x 8 Bit | |
| Mount Type | Surface | |
| Maximum Clock Frequency | 133MHz | |
| Cell Type | NOR | |
| Minimum Supply Voltage | 2.7V | |
| Maximum Supply Voltage | 3.6V | |
| Minimum Operating Temperature | -40°C | |
| Maximum Operating Temperature | 105°C | |
| Width | 5.28 mm | |
| Height | 1.9mm | |
| Length | 5.28mm | |
| Standards/Approvals | No | |
| Number of Bits per Word | 8 | |
| Series | S25FL128L | |
| Maximum Random Access Time | 8ns | |
| Number of Words | 16M | |
| Automotive Standard | AEC-Q100 | |
| Välj alla | ||
|---|---|---|
Brand Infineon | ||
Product Type Flash Memory | ||
Memory Size 128MB | ||
Interface Type Quad-SPI | ||
Package Type SOIC | ||
Pin Count 8 | ||
Organisation 16M x 8 Bit | ||
Mount Type Surface | ||
Maximum Clock Frequency 133MHz | ||
Cell Type NOR | ||
Minimum Supply Voltage 2.7V | ||
Maximum Supply Voltage 3.6V | ||
Minimum Operating Temperature -40°C | ||
Maximum Operating Temperature 105°C | ||
Width 5.28 mm | ||
Height 1.9mm | ||
Length 5.28mm | ||
Standards/Approvals No | ||
Number of Bits per Word 8 | ||
Series S25FL128L | ||
Maximum Random Access Time 8ns | ||
Number of Words 16M | ||
Automotive Standard AEC-Q100 | ||
The FL-L family connects to a host system via a Serial Peripheral Interface (SPI). Traditional SPI single bit serial input and output (Single I/O or SIO) is supported as well as optional two bit (Dual I/O or DIO) and four bit wide Quad I/O (QIO) and Quad Peripheral Interface (QPI) commands. In addition, there are Double Data Rate (DDR) read commands for QIO and QPI that transfer address and read data on both edges of the clock. The architecture features a Page Programming Buffer that allows up to 256-bytes to be programmed in one operation and provides individual 4KB sector, 32KB half block, 64KB block, or entire chip erase. By using FL-L family devices at the higher clock rates supported, with Quad commands, the instruction read transfer rate can match or exceed traditional parallel interface, asynchronous, NOR Flash memories, while reducing signal count dramatically. The FL-L family products offer high densities coupled with the flexibility and fast performance required by a variety of mobile or embedded applications. Provides an ideal storage solution for systems with limited space, signal connections, and power.
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