Microchip LAN8650B1T-E/LMX, Ethernet Transceiver, 100Mbps, Serial-SPI, 1.2 V, 24-Pin VQFN
- RS-artikelnummer:
- 333-087
- Tillv. art.nr:
- LAN8650B1T-E/LMX
- Tillverkare / varumärke:
- Microchip
Antal (1 rulle med 5000 enheter)*
235 455,00 kr
(exkl. moms)
294 320,00 kr
(inkl. moms)
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- Leverans från den 06 februari 2026
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Enheter | Per enhet | Per rulle* |
|---|---|---|
| 5000 + | 47,091 kr | 235 455,00 kr |
*vägledande pris
- RS-artikelnummer:
- 333-087
- Tillv. art.nr:
- LAN8650B1T-E/LMX
- Tillverkare / varumärke:
- Microchip
Specifikationer
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Lagstiftning och ursprungsland
Produktdetaljer
Hitta liknande produkter genom att välja ett eller flera attribut.
Välj alla | Attribut | Värde |
|---|---|---|
| Brand | Microchip | |
| Physical Network Type | IEEE802.3 | |
| Host Interface | Serial-SPI | |
| Communication Mode | Half Duplex | |
| Data Rate | 100Mbps | |
| Package Type | VQFN | |
| Pin Count | 24 | |
| Typical Operating Supply Voltage | 1.2 V | |
| Välj alla | ||
|---|---|---|
Brand Microchip | ||
Physical Network Type IEEE802.3 | ||
Host Interface Serial-SPI | ||
Communication Mode Half Duplex | ||
Data Rate 100Mbps | ||
Package Type VQFN | ||
Pin Count 24 | ||
Typical Operating Supply Voltage 1.2 V | ||
- COO (Country of Origin):
- TH
The Microchip LAN8650 combines a Media Access Controller and an Ethernet PHY to enable low‑cost microcontrollers, including those without an onboard MAC, to access 10BASE‑T1S networks. The common standard Serial Peripheral Interface of the LAN8650 allows interfacing with nearly any microcontroller, so that the transfer of Ethernet packets and LAN8650 control/status commands are performed over a single, serial interface. SPI also requires only 4 pins, enabling a simpler hardware interface with fewer pins than MII or RMII.
Internal wall clock
Event generation and event capture synchronized to the wall clock
Phase adjuster for the wall clock to minimize microcontroller overhead
Packet timestamping
Half duplex point to point link segments up to at least 15m
Event generation and event capture synchronized to the wall clock
Phase adjuster for the wall clock to minimize microcontroller overhead
Packet timestamping
Half duplex point to point link segments up to at least 15m
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