Toshiba, Decoder, 16-Pin SOIC
- RS-artikelnummer:
- 171-3382
- Tillv. art.nr:
- 74HC138D
- Tillverkare / varumärke:
- Toshiba
Antal (1 rulle med 2500 enheter)*
4 072,50 kr
(exkl. moms)
5 090,00 kr
(inkl. moms)
GRATIS leverans för online beställningar över 500,00 kr
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- Dessutom levereras 7 500 enhet(er) från den 02 februari 2026
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Enheter | Per enhet | Per rulle* |
|---|---|---|
| 2500 + | 1,629 kr | 4 072,50 kr |
*vägledande pris
- RS-artikelnummer:
- 171-3382
- Tillv. art.nr:
- 74HC138D
- Tillverkare / varumärke:
- Toshiba
Specifikationer
Datablad
Lagstiftning och ursprungsland
Produktdetaljer
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Välj alla | Attribut | Värde |
|---|---|---|
| Brand | Toshiba | |
| Logic Family | 74HC | |
| Product Type | Decoder | |
| Number of Inputs | 3 | |
| Logic Function | Decoder | |
| Mount Type | Surface | |
| Package Type | SOIC | |
| Pin Count | 16 | |
| Number of Outputs | 34 | |
| Minimum Supply Voltage | 2V | |
| Maximum Supply Voltage | 6V | |
| Minimum Operating Temperature | 125°C | |
| Maximum Operating Temperature | -40°C | |
| Width | 4 mm | |
| Height | 1.75mm | |
| Length | 10.2mm | |
| Standards/Approvals | No | |
| Series | 74HC | |
| Automotive Standard | No | |
| Välj alla | ||
|---|---|---|
Brand Toshiba | ||
Logic Family 74HC | ||
Product Type Decoder | ||
Number of Inputs 3 | ||
Logic Function Decoder | ||
Mount Type Surface | ||
Package Type SOIC | ||
Pin Count 16 | ||
Number of Outputs 34 | ||
Minimum Supply Voltage 2V | ||
Maximum Supply Voltage 6V | ||
Minimum Operating Temperature 125°C | ||
Maximum Operating Temperature -40°C | ||
Width 4 mm | ||
Height 1.75mm | ||
Length 10.2mm | ||
Standards/Approvals No | ||
Series 74HC | ||
Automotive Standard No | ||
The 74HC138D is a high speed CMOS 3-to-8 DECODER fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. When the device is enabled, 3 Binary Select inputs (A, B and C) determine which one of the outputs (Y0 - Y7) will go low. When enable input G1 is held low or either G2A or G2B is held high, decoding function is inhibited and alloutputs go high.G1, G2A, and G2B inputs are provided to ease cascade connection and for use as an address decoder for memory systems. All inputs are equipped with protection circuits against static discharge or transient excess voltage
High speed: tpd = 16 ns (typ.) at VCC = 5 V
Low power dissipation: ICC = 4.0 μA (max) at Ta = 25
Balanced propagation delays: tPLH ≈ tPHL
Wide operating voltage range: VCC(opr) = 2.0 to 6.0 V