Nexperia 74HCT138D,653, Decoder, 16-Pin SO16
- RS-artikelnummer:
- 170-4849
- Tillv. art.nr:
- 74HCT138D,653
- Tillverkare / varumärke:
- Nexperia
Antal (1 rulle med 2500 enheter)*
5 555,00 kr
(exkl. moms)
6 945,00 kr
(inkl. moms)
Lagerinformation är för närvarande otillgänglig
Enheter | Per enhet | Per rulle* |
|---|---|---|
| 2500 + | 2,222 kr | 5 555,00 kr |
*vägledande pris
- RS-artikelnummer:
- 170-4849
- Tillv. art.nr:
- 74HCT138D,653
- Tillverkare / varumärke:
- Nexperia
Specifikationer
Datablad
Lagstiftning och ursprungsland
Produktdetaljer
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Välj alla | Attribut | Värde |
|---|---|---|
| Brand | Nexperia | |
| Mounting Type | Surface Mount | |
| Package Type | SO16 | |
| Pin Count | 16 | |
| Dimensions | 6.4 x 5.4 x 1.8mm | |
| Maximum Operating Supply Voltage | 5.5 V | |
| Maximum Operating Temperature | +125 °C | |
| Minimum Operating Temperature | -40 °C | |
| Minimum Operating Supply Voltage | 4.5 V | |
| Välj alla | ||
|---|---|---|
Brand Nexperia | ||
Mounting Type Surface Mount | ||
Package Type SO16 | ||
Pin Count 16 | ||
Dimensions 6.4 x 5.4 x 1.8mm | ||
Maximum Operating Supply Voltage 5.5 V | ||
Maximum Operating Temperature +125 °C | ||
Minimum Operating Temperature -40 °C | ||
Minimum Operating Supply Voltage 4.5 V | ||
- COO (Country of Origin):
- TH
The 74HC138, 74HCT138 decodes three binary weighted address inputs (A0, A1 and A2) to eight mutually exclusive outputs (Y0 to Y7). The device features three enable inputs (E1, E2 and E3). Every output will be HIGH unless E1 and E2 are LOW and E3 is HIGH. This multiple enable function allows easy parallel expansion to a 1-of-32 (5 to 32 lines) decoder with just four 138 ICs and one inverter. The 138 can be used as an eight output demultiplexer by using one of the active LOW enable inputs as the data input and the remaining enable inputs as strobes.
Multiple input enable for easy expansion or independent controls
Integrated input latch to store the address of decoder lines
Ideal for memory chip select decoding
Asynchronous and synchronous load options
Overvoltage tolerant input options
Inverting and non-inverting output options
3-stage outputs
High frequency
Can be cascaded
Key applications
Selection of memory banks and peripherals
I/O expansion
Integrated input latch to store the address of decoder lines
Ideal for memory chip select decoding
Asynchronous and synchronous load options
Overvoltage tolerant input options
Inverting and non-inverting output options
3-stage outputs
High frequency
Can be cascaded
Key applications
Selection of memory banks and peripherals
I/O expansion
