Altera DK-START-5AGXB3N Arria V GX Starter Kit 5AGXFB3H4F35C5N

The Altera Arria® V GX FPGA Starter Kit includes all the hardware and software you need to develop cost-sensitive FPGA applications immediately. It features a High-Definition multimedia interface (HDMI) and Serial Digital Interface (SDI) connectors.

FPGA
Arria V GX 5AGXFB3H4F35C5N
System controller: MAX V 5M2210ZF256C4N device
Power monitor GUI
Analogue-to-digital converter (ADC) with eight channels
Non-isolated power rail
Fast passive parallel (FPP) x16 mode through parallel Flash loader (PFL)
Control and status registers
Embedded USB-Blaster II: MAX II EPM570GM100C4N device
HDMI 1.3 TX
4 x XCVR, 2.7Gbps (max by level shifter) and 270MHz Tx clock HDMI Tx connector
STMicroelectronics HDMI level shifter STHDLS101T
Level shift XCVR PCML 1.5V <-> TMDS level
DDC and HPD <-> HDMI compliant level
Data channel up to 2.7Gbps; HDMI 1.3 compliant
Clock channel up to 270MHz; enough to support 2.7Gbps data rate
HDMI specification: clock period = 10x of UI
SDI 3G
XCVR Tx/Rx loopback
2 x SMB connectors (cable not included in kit)
Up to 2.97Gbps
Uses National Semiconductor driver/receiver LMH0384SQ/LMH0303SQx
Requires 148.5MHz and 148.35MHz at XCVR refclk to support US and EU standard respectively
Use VCXO to fine tune and lock to the recovered CDR frequency
HSMC
8 x XCVR up to 6.375Gbps
Not compliant to PCI Express (PCIe) HIP pin assignment
4 x CMOS
8 x Tx and 9 x Rx differential interface using dedicated Tx/Rx channels
2 x low-voltage differential signalling (LVDS) clock in
2 x differential clock out
I2C bus
JTAG
Minimum current support: 2A @ 3.3V, 1A @ 12V
Dedicated clock domain from Si 5338 clock generator for xcvr refclk
HSMC loopback with BTS GUI
SMA
XCVR Tx/Rx channel
LVPECL clock input
LVPECL clock output
Dedicated clock domain from Si 5338 clock generator for xcvr refclk
DDR3 SDRAM
Micron MT41J64M16LA-15E DDR3 SDRAM 8M x 16 x 8
Two devices: 2 x 16 width = x32
BTS DDR3 SDRAM GUI using Uniphy and high performance (HP) controller II
SSRAM
512K x 36, 18Mb ISSI IS61VPS51236A
Shared address or data with Flash
User IO
LCD character display
4 x DIP switch
3 x pushbuttons
4 x LEDs
Configuration
FPP x16 mode
Dual Flash 512Mbit Numonyx PC28F512P30BF (52MHz fMAX)
JTAG header
Embedded USB Blaster II
Cypress Microcontroller CY7C68013A as USB PHY 2.0
MAX II device
Ethernet
10/100/1000 Base-T
RJ-45 connector, on-board LED for link status
Marvell Ethernet PHY 88E1111
Requires 50MHz clock from CLKIN

Loopback and debug header daughter cards, USB cable, 75Ω SMB video cable, Ethernet cable, license for the Development Kit Edition (DKE) of the Quartus II software (Windows platform only).

An FPGA is a semiconductor device consisting of a matrix of Configurable Logic Blocks (CLBs) connected through programmable interconnects. The user determines these interconnections by programming SRAM. A CLB can be simple (AND, OR gates, etc) or complex (a block of RAM). The FPGA allows changes to be made to a design even after the device is soldered into a PCB.